Case Study-AMBA Protocol (Prajakta)

Verification of AMBA Bus

AMBA - advanced microcontroller  bus architecture , it is on chip communication standard designing for high performance .AMBA is a solution for the blocks to interface with each other. so there are in total  3 Types  of buses of AMBA  as follows:- 

        1. AHB - advance high performance 

        2. ASB- advance system bus 

        3. APB- advance peripheral bus.




When talking of the difference between the AHB and APB , the AHB uses a full duplex parallel communication whereas the APB uses massive memory-I/O accesses, When comparing the usage, the APB is simpler than the AHB. Unlike the AHB, there is no pipelining in APB. The APB is mainly proposed for connecting to simple peripherals. Looking at the AHB and the APB, it can be seen that the APB comes with a low power peripheral.

Functional Verification of the Axi2ocp Bridge using System Verilog and effective bus utilization calculation for AMBA AXI 3.0 Protocol .

 

Functional verification plays a key role in validating a design and its Functionality.AXI20CP Bridge connects two different protocols i.e. advanced extensible interface and open core protocol. AXI20CP Bridge helps in converting AXI 3.0 format signals to OCP format signals, AXI address to OCP address and AXI data to OCP data. Protocols With effective Bus utilization leads to have a faster data rate with increased performance. Measuring the Bus utilization parameter for the AXI 3.0 protocols generated test cases and functional verification of the AXI20CP Bridge using system verilog language is the main idea of this paper

 

Different types of test cases generated are as follows:

 1) Read phase which includes two channels i.e. read address and read data plus response channels are verified in this case with the help of obtained waveforms. Bus utilization for this test case is 76.92%.

 2) Write phase which includes three channels i.e. write address, write data and write response channels. Write phase is divided into three channels response. The necessity to verify write phase is whether hand shaking of signals is happening perfectly or not in all the three channels. Bus utilization for this case is 81.25% .

TEST CASE

Valid count

Busy count

Bus utilization

Read phase

10

13

76.92%

Write phase

13

16

81.25%

Write read phase

42

44

95.45%

 

 

 

 





3) Write _read phase which includes the entire write and read channels i.e. totally five channels are verified in this test case taking bus utilization into consideration. Bus utilization for this case is 95.45%.


Analysis of LEON3 Systems Integration for a Network-on-Chip.


The LEON processor is a softcore for space applications .The interconnection of components in a LEON3-based system is performed by means of the ARM AMBA 2.0 bus, using the AHB protocol for the high-performance cores and the APB protocol for peripherals. However, bus architecture does not meet the communication requirements of systems. AMBA 2.0 bus as an on-chip communication.





Architecture

FFs

Fmax

Power

 Standard

  

1,238

61.82MHz

203.79mW

Network interface connected to the bus

 

1,859

63.79MHz

251.53mW

Network interface connected to the cores

 

1,536

65.75MHz

242.36mW

 

This paper presented comparative analysis of three systems architectures for the integration of the LEON3 processor in an embedded system, bus-dependent approach and direct connection between an interface and the cores were analyzed.





 

 

 

 

 

 

 

 

 

 

 

 

 

 



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