Case study on design of AMBA bus protocol (Pradnya)

Effective Design and Implementation of AMBA AHB Bus Protocol using Verilog [Deeksha 2019]

In the modern era of VLSI technology, the processing devices depend on the communication protocol System-On Chip (SOC). The Advanced Microcontroller Bus Architecture (AMBA) was presented by ARM Ltd in 1996 and it is widely used as an on-chip bus in the system (SoC) outlines.

Advanced System Bus (ASB) and Advanced Peripheral Bus (APB) were the main AMBA buses. The AHB bus is designed for high-performance, high-clock system modules thus acts as the system's high-performance backbone bus. In the third era, AMBA 3, included AXI, which achieves significantly higher execution interconnections and the Advanced Trace Bus (ATB) as a major aspect of the Core Sight on-chip troubleshooting and trace solution.

An AMBA-based microcontroller usually consists of a AHB bus that supports the CPU's external memory bandwidth, on-chip memory and other DMA devices.


A typical AMBA Advanced High-performance Bus system design the following components:

  1. AHB Master:  A master initiates the reading / writing operation by providing the arbitrator with the control information and the slave's address.
  2. AHB Slave: An AHB bus slave responds to transfers made by bus masters inside the system. The slave uses a signal to select the HSELx decoder to determine when to respond to a bus transfer.
  3. AHB Arbiter: The bus arbiter ensures only a single bus master at a time initiates a data transfer.
  4.  AHB Decoder: An AHB decoder is used to decode the address of each transfer and provide the appropriate signal for the slave that is involved in the transfer.

Verification Of AHB_LITE Protocol For Waited Transfer Responses Using Re-Usable Verification Methodology [Srinivas 2016]

Verification plays a major role in the implementation of SOC and it is as important as designing. AHB-LITE is the part of the AHB protocol to meet the requirements of high performance synthesizable designs. This subpart of the protocol simplifies the design for a bus which works with only a single master. Universal Verification Methodology is related to System Verilog, which is the latest and a well demanded methodology used in VLSI industry for verification of the SoCs and Digital Systems. OVM and VMM are some of the other methodologies that are followed in the industry. With UVM has made an industry standard now, this methodology is supported by all EDA tools and hence testbenches written in UVM verification environment can be verified on any EDA tool without any tool vendor-dependent issues. 
AHB_LITE Block Diagram


AHB-LITE PROTOCOL SYSTEM
  • AMBA AHB_LITE bus protocol is a part of the AHB bus protocol, where its operates only with single master and multiple slaves. The block diagram of the AHB_LITE shows a single master and three slaves along with the memory map address decoder and multiplexor are used for bus interconnections as shown in Fig .
  • The decoder is used to select the appropriate slave in order to store the data, with the information coming from the master and routes the same information to the multiplexor to get output response from the respective slave to master. 

OPERATIONS OF AHB-LITE 
  • The AHB_LITE initiates the operation by transferring the address and control information. These control information gives the whether to perform write or read operation, amount of bytes to be transferred with the type of burst. Every transfer performs operation with two phases called address and data phase.

Various Arbitration Algorithm for On-Chip(AMBA) Shared Bus Multi-Processor SoC [Shrivastava 2016]

Performance of Multi core Shared bus Embedded Controller depends on how effectively the sharing resources can be utilized. Common bus in System on Chip is one of the sharing resources, shared by the multiple master cores and also acting as a channel between master core and slave core (peripherals) or Memories. Arbiter is an authority to use the shared Resource (Shared bus) effectively, so performance also depends on arbitration techniques. The arbitration mechanism is used to ensure that only one master has access to the bus at any one time. The arbiter performs this function by observing a number of different requests to use the bus. Master may request to bus master (arbiter) to use the bus during any cycle. The arbiter will sample the request on the rising of the clock and then use predefined algorithm to decide which master will be the next to gain access to the bus.



The topology consists of combination of shared buses and dedicated channels to which various SoC components are connected. The SoC components include (1) components that initiates transaction called Masters (2) components that respond to transactions initiated by masters called Slaves that includes memories and peripheral devices. Since shared bus is used by SoC bus architectures should be designed in such a way to manage access to the bus, which are implemented in bus Arbiter. Arbitration is a mechanism that decides the owner of a shared resource .



The communication architecture topology consists of a network of shared and dedicated communication channels, to which various SoC components are connected. These include (i) masters, (e.g., CPUs, DSPs, DMA controllers etc.), and (ii) slaves, (e.g., on-chip memories). When the topology consists of multiple channels, bridges are used to interconnect the necessary channels. Since buses are often shared by several SoC masters, bus architectures require protocols to manage access to the bus ,which are implemented in (centralized or distributed) bus arbiters. 
 








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