Case study on AMBA bus design (Achal)

  • Design of an Advanced Microcontroller Bus Architecture for Wireless Sensor Network in 90nm Process Technology[2018]

 AMBA- Advance microcontroller bus architecture is mostly preferred in senseIT development. AMBA is opensource, on-chip interface specification for connection and functional blocks in SOC system. This bus is most efficient in transferring data from block to block with low power consumption. For wireless sensor network AHB-lite is suitable as it has only one master and provide high performance.

The design flow graph for AHB-lite in 90 nm technology is initiated with representation of system in blocks and then RTL(Register Transfer Level) is written for the AMBA (AHB-lite) in Verilog HDL. Then it undergoes for verification which ensures the accuracy and then it get synthesize. For verification Universal Verification Method (UVM) is used. After synthesis, the RTL of Amba is translated into gate level netlist. 

  •   RTL Implementation of AMBA ASB APB Protocol at System on Chip Level[2015]

The system on chip describes the implementation of whole system on a single chip. AMBA is considered as most important on chip bus. For implementation of AMBA bus the Verilog and Finite state machine methodology is used.



Above figure shows complete arrangement of AMBA configuration, in which left side work for high bandwidth peripheral while right side for low bandwidth peripheral. ASB (advance system bus) used for high performance pipelines and  giving access to the multiple master. And the APB (Advance peripheral bus ) provides address, data(read/ write) and control signal (master or slave configuration )  for connected peripherals. 

 Implementation is  done in 3 parts. First APB bridge designed is considered as it is only master for all APB buses. State machine is design to implement  the bridge with ASB bus without considering  latching and memory mapping issue. And its operation is verified with the help modelsim. Next, multiple masters leads to the cross couple of data so arbitration is provided between the master for  ensuring one master to communicate at one time. Third one is decoder. The default decoder insert decoding cycles before slave response. Theses cycle are automatically inserted as start of non-sequential transfer or  as non-sequential transfer blast asserted.

After this specification writing and review is done. And RTL view of AMBA bus is generated. Then RTL description is simulated and synthesized. After gate-level net-list is completed and the power summary  is analyze with help of Xpower Analyzer.

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  • Design of AXI bus interface modules on FPGA[2016]
 ARM cortex processor needs high speed operation which can be maintain  with help of AXI protocol as it targeted to have high performance and high clock frequency operation. The AXI specifies the descriptions of signal, channel handshaking, addressing options and response for data transferring. The AXI protocol has master interface, interconnect, and the slave interface. It uses five different channels for reading, writing, responding of data. The interconnect has blocks such as Arbiter, decoder, master controller, slave controller.

There are 2 arbiters in an interconnect. They serve one master to read and another to write at a same time as one arbiter is for write group of channels and other for read group of channels. The decoder works for obtaining the slave address which basically gives memory location for read and write operation. There is total five decoder for five different channels. Master controller performs the function of multiplexing and demultiplexing of signal from grant master to slave controller and slave controller to input bus of grant master with arbiter control signal respectively. Similarly, slave controller multiplex and demultiplex the output bus signal from slave to master and master to slave with the help of decoder control signal.

The AXI bus is design with 100MHz frequency and simulated using Xilinx and modelsim. And all modules are synthesized on sparte3 FPGA



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