Case Study-AMBA Protocol (Shrutak)

What is AMBA Bus?

The advanced micro-controller Bus Architecture (AMBA) bus protocol is an on-chip communication mechanism between various functional blocks for building high-performance SOC design. This design has one or more micro-controller or microprocessors along with several other components i.e. USB, UART,12C, etc all integrated on a single chip. The primary motivation of AMBA protocol is to have a standard and efficient way to interconnect these blocks.

The following diagram illustrates AMBA-based SOC design that uses the AHB (Advanced High-performance Bus) or ASB (Advanced System Bus) protocols for high bandwidth interconnect and APB (Advanced Peripheral Bus) protocols for low bandwidth peripherals interconnects.  

Need Of AMBA Bus

Integrated circuits have entered the era of System-on-a-Chip (SoC), which refers to integrating all components of a computer or other electronic system into a single chip. With the increasing design size, IP is an inevitable choice for SoC design making On-Chip Buses (OCB) essential to the design. Of all OCBs existing in the market, the AMBA bus system is widely used as the de facto standard SoC bus.

On March 8, 2010, ARM announced the availability of the AMBA 4.0 specifications. As the de facto standard SoC bus, the AMBA bus is widely used in high-performance SoC designs. The AMBA specification defines an on-chip communication standard for designing high-performance embedded microcontrollers. The AMBA 4.0 specification defines five buses/interfaces.

Advanced eXtensible Interface (AXI)

• Advanced High-performance Bus (AHB)

• Advanced System Bus (ASB)

 • Advanced Peripheral Bus (APB)

Advanced Microcontroller Bus Architecture defines the on-chip communication standard for designing high-performance embedded microcontrollers. Three types of buses are defined in AHB specification by ARM, they are Advanced High-Performance Bus (AHB), Advanced System Bus (ASB) and Advanced Peripheral Bus (APB).

An AMBA-based microcontroller contains a high-performance system bus (AMBA AHB or ASB), on-chip memory, CPU cores, and DMA (Direct Memory Access) devices. APB is a secondary bus or peripheral bus that provides communication between peripheral devices.

AHB is a generation of AMBA bus which supports multiple Bus Masters and slaves, provide high- Bandwidth operation and high-performance synthesizable design. The unique feature of AHB for high performance is burst transfer, pipelined operation, Multiple bus master and split transaction. AHB master initiates read/write operation by providing address & control information. Only 1 bus master allowed to actively use the bus at a time. Max of 16 masters is allowed. Slave responds to read/write operations. It signals back to the active master about success, failure, or waiting for data transfer. Arbiter controls which bus master has access to use the bus. It selects master based on the prioritization (default round-robin). The decoder is a centralized decoding function.

 

AMBA AHB signal

Name		Source
HCLK	Bus Clock	Clock source
HRESETn	Reset	Reset controller
HADDR[31:0]	Address Bus	Master
HTRANS[1:0]	Transfer Type	Master
HWRITE	Transfer direction	Master
HSIZE	Transfer size	Master
HBURST	Burst type	Master
HPROT	Protection control	Master
HWDATA	Write Data bus	Master
HSELx	Slave select	Decoder
HRDATA[31:0]	Read data bus	Slave
HREADY	Transfer Done	Slave
HRESP	Transfer response	Slave
HBUSREQx	Bus request	Master
HLOCKx	Locked Transfer	Master
HGRANTx	Bus grant	Arbiter
HMASTER[3:0]	Master number	Arbiter
HMASTLOCK	Locked sequence	Arbiter
HSPILTx	Split compilation request	Slave split capable