Case Study On AMBA Bus Protocol (Sanjana)

Hard Real Time Bus Architecture and Arbitration Based On AMBA [Liang 2015]


Real time data processing means the implementation of data in a short stretch of time providing an immediate output. This makes it a prime reason for using it in many of the VLSI or embedded system applications. It is very important to design a high-speed real time bus structure in real time systems considering that the time spent in data transfer among the devices is much more than the time used for computation and operation.  A real time bus employs lot of techniques to satisfy real-time requirements. This kind of an architecture is acquired by achieving high bandwidths, which relieves the issue with heating by increasing the frequency. To improve efficiency, hardware is adopted as it requires less delay and complexity than software. This architecture guarantees that the time cost by every task, including the time waiting for service, is predictable. This brings AMBA as a protocol into the picture. AMBA stands for Advanced Microcontroller Bus Architecture.





Arbitration mechanism :
A single bus structure enables many devices to send requests at the same time whereas a multi bus protocol devices send requests only to the same source.
such situations result in conflicts hence bus arbitration is needed in order to resolve the conflict. This mechanism determines the priority of each device sending a  request and consequently the device with highest priority is able to acquire the target.
There are two such kind of implementation mechanisms:
1) a centralized mechanism integrates or collects all controlling logic into one module which is known as the central arbiter.
2) distributed mechanism assigns an arbiter for every resource that exists in the network . 
the centralized mechanism is generally preferred in order to avoid conflicts as choices are made from a global point of view .

Arbitration algorithms are categorized as:
1) static algorithm 
2) dynamic algorithm 
3) hybrid 
Static algorithm utilizes fixed priority of resources.
Dynamic algorithm is further categorized as TDM and Lottery.
A popularly used hybrid algorithm is known as Daisy chain algorithm


Design of High Performance Master/Slave Memory Controller for Grey scale Image transfer [Bevoor 2017]


For the case study, we will look at a memory controller for image transfer designed by Sweta Bevoor and Prasanth Gowda in 2017. They had proposed the design of an AMBA compliant for memory controller to facilitate the grey scale image transfer across two slaves. The memory controller would be designed to provide high performance and frequency for this transfer of images between the memory and integral blocks of the AMBA. The transfer is performed by combining the processing of the image and the black box of the memory controller. A selected line would choose either of the two slaves to hold the grey scale image output of the image transfer.

 

The protocol used is the AMBA/AHB protocol in burst/normal mode supporting multiple masters and slaves. Every communication along the bus has an address and control information associated with it. This determines the nature of data that needs to be transferred across the memory controller. The master communication includes an address and control signals which directs it to respective slaves. A signal multiplexer selects the slave involved in the transfer of image and forwards the selected input to the other slave chosen for output.

 

The AHB has two phases:

              1. Address phase - exists for a single cycle

              2. Data phase - exists for several cycles

The master responds at every rising edge of the clock in the simple transfer, i.e. between a singular master and slave. In return, the slave detects the master signals at every consecutive rising edge of the clock. Although AHB supports multiple transfers, i.e. between multiple masters and slaves, for the purpose of their project, a single master with two slaves are used for simple image transfers.


Design And Simulation of Multimaster AHBLite Bus Interconnect [Ingle 2017]


The on chip bus system generally uses the AMBA protocol which was developed by ARM and is the most widely used. This protocol further simplifies the block design by utilizing a combination of blocks that are interchangeable in SoC design. These blocks which are known as intellectual property blocks are reused in SoC design , thereby reducing the time required to market in SoC design. 

AMBA defines three kinds of Bus systems:

1) Advanced high performance bus system (AHPB)

2) Advanced system bus (ASB)

3) Advanced Peripheral Bus system (APB)

A newly developed kind of AMBA is known as  AMBA AHB which is used in designs that require a high performance. AMBA AHB is a type of performance high system that can support multiple bus masters and provides each one a high bandwidth .

Few features are :

1) Burst transfer 

2) Split transaction 

3) Data width support which can range from 32 to 1024 bits 


A system can be designed using AMBA AHB that can contain one or more bus masters. Each system typically consists of one processor and one test interface.Commonly used AHB slaves are APB bridge, internal and external memory interfaces and other peripherals .

Therefore an AMBA AHB system consists of :

1) AHB master

2) AHB slave 

3) AHB decoder 


AMBA AHBLite 

It is a kind of subset of full AHB that requires of a single bus master. It can also be a single or multiple layer system in which each layer is defined according to protocol . This system also removes the grant /request protocol which is required for multiple bus master systems , split or slave response therefor simplifying AHB specifications.

Few features :

1) Burst transfers 

2) Data bits ranging from 32 to 1024 bits 

AHBLITE slaves are very similar to AMBA AHB slaves in terms of high bandwidth , internal and external peripherals and external memory interfaces. Connecting a peripheral to a higher level system bus can be done using an APB bridge that is a AHBLite slave.


Performance Exploration of AMBA AXI4 Bus Protocols for Wireless Sensor Networks [ Makni 2017]


AMBA AX14 on chip protocol for communication between the CPU and FPGA is supported by Xilinx’s ZYnq -7000 devices. The latest version of AMBA AX14 protocol is AMBA standard. It is specifically used for high performance data transfer and high frequency SoC designs . 

According to figure 1, three different interfaces are defined by AMBA 4 protocol : stream, burst and lite. each interface consists of advanced features like burst and pipelining transfers and is used for data exchange between the CPU and HAs. This section represents an overview of on-chip interconnects and different HLS optimization programs utilized a subset of full AX14 specification is AX14 Lite. It is useful for simple and low power performance devices such as UartLite, GPIO etc. The transfer length is fixed for one data transfer. ARM processor acts as master making HA the slave in a typical AX14 lite design 

ARM processor that acts as the master controls the system and is responsible for transferring data to the HA block through R/W ops . Initially the CPU sends the address to the HA to be read in order to obtain input data. The slave has to be immediately respond to a transfer request , if not the master is stalled . 

1) Through AX14 lite simple components can be connected via small interfaces that require less design and effort . A simple control register is utilized by such interfaces that does not allow for burst data transfer .

2) AX14 burst interface has a maximum length of 256. A large length enables integration of the devices with large block transfers . This interface also supports multiple region interfaces . An ARM processor consists of a main memory (DDR memory ) to store application data . Each HA has a local RAM memory that is used to store data locally produced .

3) AX14 stream interface : this protocol has an efficient interface for non address-based communication in master slave architecture. The interface was originally created for high speed data transfer to destinations which are not internally memory -mapped . The data length here is not restricted in comparison to AX14 burst interface



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